1. Field of the Invention
The present invention pertains to a method of controlling the film properties of a silicon nitride film deposited by PECVD (plasma-enhanced chemical vapor deposition) over a substrate having a large surface area, and to the film deposited by the method. In particular, the uniformity of the density of the silicon nitride film across the substrate surface is improved by controlling the film-forming precursors.
2. Brief Description of the Background Art
Current interest in thin film transistor (TFT) arrays is particularly high because these devices are used in liquid crystal active matrix displays of the kind often employed for computer and television flat panels. The liquid crystal active matrix displays may also contain light emitting diodes for back lighting. Further, organic light emitting diodes (OLEDs) have been used for active matrix displays, and these organic light emitting diodes require TFTs for addressing the activity of the displays.
The TFT arrays are typically created on a flat substrate. The substrate may be a semiconductor substrate, or may be a transparent substrate such as glass, quartz, sapphire, or a clear plastic film. The TFT which is the subject of the present invention employs silicon-containing films, and in particular employs silicon nitride containing films for dielectric layers. A first silicon nitride-comprising film is referred to as the gate dielectric because it overlies the conductive gate electrode. A second silicon nitride-comprising film is referred to as the passivation dielectric and overlies the upper surface of a second conductive electrode, to electrically isolate the second conductive electrode from the ambient surrounding the upper surface of the TFT device (where the lower surface of the TFT device is the glass, quartz, sapphire, plastic, or semiconductor substrate).
FIG. 1 illustrates a schematic cross-sectional view of a thin film transistor structure of the kind which may employ both a silicon nitride-comprising gate dielectric film and a silicon nitride-comprising passivation dielectric film. This kind of thin film transistor is frequently referred to as an inverse staggered α-Si TFT, with a SiNx layer as a gate insulator or as a back channel etch (BCE) inverted staggered (bottom gate) TFT structure. This structure is one of the more preferred TFT structures because the gate dielectric (SiNx) and the intrinsic as well as n+ (or p+) doped amorphous silicon films can be deposited in a single PECVD pump-down run. The BCE TFT shown in FIG. 1 involves only four or five patterning masks.
As previously mentioned, the substrate 101 typically comprises a material that is essentially optically transparent in the visible spectrum, such as glass, quartz, sapphire, or a clear plastic. The substrate may be of varying shapes or dimensions. Typically, for TFT applications, the substrate is a glass substrate with a surface area greater than about 500 mm2. A gate electrode layer 102 is formed on the substrate 101. The gate electrode layer 102 may comprise a metal layer such as, for example, aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), molybdenum (Mo), molybdenum tungsten (MoW), titanium (Ti), or combinations thereof, among others. The gate electrode layer 102 may be formed using conventional deposition, lithography, and etching techniques. Between the substrate 101 and the gate electrode layer 102, there may be an optional (not shown) insulating layer, for example, such a silicon oxide, or silicon nitride, which may also be formed using a PECVD system of the kind which will be described later herein.
A gate dielectric layer 103 is formed on the gate electrode layer 102. The gate dielectric layer may be silicon oxide, silicon oxynitride, or silicon nitride, deposited using such a PECVD system. The gate dielectric layer 103 may be formed to a thickness in the range of about 100 Å to about 6000 Å.
A bulk semiconductor layer 104 is formed on the gate dielectric layer 103. The bulk semiconductor layer 104 may comprise polycrystalline silicon (polysilicon), microcrystalline silicon (μc-Si), or amorphous silicon (α-silicon), which films can also be deposited using a PECVD system, or other conventional methods known in the art. Bulk semiconductor layer 104 may be deposited to a thickness in the range of about 100 Å to about 3000 Å. A doped semiconductor layer 105 is formed on top of the semiconductor layer 104. The doped semiconductor layer 105 may comprise n-type (n+) or p-type (p+) doped polycyrstalline, microcrystalline, or amorphous silicon. Doped semiconductor layer 105 may be deposited to a thickness within a range of about 100 Å to about 3000 Å. An example of the doped semiconductor layer 105 is n+ doped α-silicon film. The bulk semiconductor layer 104 and the doped semiconductor layer 105 are lithographically patterned and etched using conventional techniques to define a mesa of these two films over the gate dielectric insulator, which also serves as storage capacitor dielectric. The doped semiconductor layer 105 directly contacts portions of the bulk semiconductor layer 104, forming a semiconductor junction.
A conductive layer 106 is then deposited on the exposed surfaces of gate dielectric layer 103, semiconductor layer 104, and doped semiconductor layer 105. The conductive layer 106 may comprise a metal such as, for example, aluminum, tungsten, molybdenum, chromium, tantalum, and combinations thereof, among others. The conductive layer 106 may be formed using conventional deposition techniques. Both the conductive layer 106 and doped semiconductor layer 105 may be lithographically patterned to define source and drain contacts of the TFT, 106a and 106b, respectively in FIG. 1. After formation of the source and drain contacts 106a and 106b, a passivation dielectric layer 107 is typically applied. The passivation dielectric layer may be, for example, a silicon oxide or a silicon nitride. The passivation layer 107 may be formed using, for example, PECVD or other conventional methods known in the art. The passivation layer 107 may be deposited to a thickness in the range of about 1000 Å to about 5000 Å. The passivation layer 107 is then lithographically patterned and etched using conventional techniques, to open contact holes in the passivation layer.
A transparent electrically conductive layer 108 is then deposited and patterned to make contacts with the conductive layer 106. The transparent conductor layer 108 comprises a material that is essentially optically transparent in the visible spectrum. Transparent conductor 108 may comprise, for example, indium tin oxide (ITO) or zinc oxide among others. Patterning of the transparent electrically conductive layer 108 is accomplished by conventional lithographic and etching methods.
There are a number of additional TFT structures which can employ silicon nitride gate insulators, and several of these are presented in a disclosure entitled “A Study on Laser Annealed Polycrystalline Silicon Thin Film Transistors (TFTs) with SiNx Gate Insulator”, by Dr. Lee Kyung-ha (Kyung Hee University, 1998). (This disclosure is available at http://tftcd.khu.ac.kr/research/polySi.) Dr. Lee Kyung-ha's disclosure pertains mainly to the use of laser annealed poly-Si TFTs, which is not the subject matter of the present invention, but the TFT structures are of interest as background material. The structures of interest are presented in Chapter 2 of the disclosure.
D. B. Thomasson et al., in an article entitled: “High Mobility Tri-Layer a-Si:H Thin Film Transistors with Ultra-Thin Active Layer”, 1977 Society for Information Display International Symposium Digest of Technical Papers, Vol. 28, pages 176-179, describe active matrix liquid crystal displays where the TFT has an active layer thickness of about 13 nm. The TFT structure is a glass substrate with a molybdenum bottom electrode, a silicon nitride gate dielectric layer, an a-Si:H layer overlying the silicon nitride gate dielectric layer, n+ μc-Si:H doped source and drain regions, separated by a silicon nitride dielectric mesa, and with an aluminum contact layer overlying each source and drain region. This is referred to as a tri-layer a-Si:H TFT structure. The authors claim that such hydrogenated amorphous silicon thin-film transistors with active layer thickness of 13 nm perform better for display applications than devices with thicker (50 nm) active layers. The linear (VDS=0.1V) and saturation region mobility of a 5 μm channel length device is said to increase from 0.4 cm2/V·sec and 0.7 cm2/V·sec for a 50 nm a-Si:H device, to 0.7 cm2/V·sec and 1.2 cm2/V·sec for a 13 mn a-Si:H layer device fabricated with otherwise identical geometry and processing. The gate dielectric silicon nitride was deposited from a reactant gas mixture of SiH4, NH3, and Ar at 100 mW/cm2, −150 V, 0.5 Torr, and 300° C. The passivation silicon nitride dielectric layer was deposited at the same conditions as the gate dielectric, with the exception of substrate temperature, which was 250° C.
Young-Bae Park et al., in an article entitled: “Bulk and interface properties of low-temperature silicon nitride films deposited by remote plasma enhanced chemical vapor deposition”, Journal of Materials Science: Materials in Electronics, Vol. 23, pp. 515-522 (2001), describe problems which occur when a gate dielectric, rather than being SiNx, is a hydrogenated silicon nitride film (a-SiNx:H). PECVD a-SiNx:H thin films are said to be widely used as a gate dielectric for a-Si:H TFT applications, due to the good interfacial property between an a-Si:H layer and an a-Si:Nx:H layer. However, the a-Si:H TFTs with SiNx:H gate dielectric are said to have instability problems, such as the threshold voltage shift and the inverse subthreshold slope under a DC gate voltage bias. Their instability problems are said to be caused by the high trap density in the SiNx:H film and the defects created at the a-Si:H/SiNx:H interface. Charge trapping in the SiN:H is said to be from the electron injection under an applied field, and due to the localized states of the Si dangling bonds, Si—H and N—H bonds in the forbidden gap. The authors claim that PECVD SiNx:H dielectric films are not useful as a gate insulator because they contain large amounts of bonded hydrogen (20%-40%) in the form of N—H and Si-H bonds.
The authors propose that a remote plasma enhanced chemical vapor deposition of the gate dielectric layer be carried out. The NH3 precursor is excited in a remote plasma zone (at the top of the chamber) to produce NH* or NH2*+H*, after which the activated species* from the plasma zone react with SiH4 introduced downstream through a gas dispersal ring to form the SiNx:H electrical insulator with a reduction in the amounts of bonded hydrogen in the form of Si—H bonds, which are said to easily lose hydrogen to form a dangling bond of the kind known to reduce performance of the TFT device over time.
A presentation entitled “Low Temperature a-Si:H TFT on Plastic Films: Materials and Fabrication Aspects”, by Andrei Sazonov et al., Proc. 23rd International Conference on Microelectronics (MIEL 2002), Vol. 2, NIS, Yugoslavia, 12-15 May 2002, related to fabrication technology for a-SiH thin film transistors at 120° C. for active matrix OLED displays on flexible plastic substrates. The TFTs produced were said to demonstrate performance very close to those fabricated at 260° C. The authors claim that with the proper pixel integration, amorphous hydrogenated silicon (a-Si:H) TFTs are capable of supplying sufficiently high current to achieve required display brightness and thus can be a cost-effective solution for active matrix OLED displays.
The silicon nitride films used to produce the fabricated TFT samples were amorphous silicon nitride deposited at 120° C. by PECVD from SiH4 and NH3 gaseous precursors. The film is said to have a lower mass density and higher hydrogen concentration in comparison with films fabricated at 260° C. to 320° C. In the study, a series of a-SiN:H films with [N]/[Si] ratio ranging from 1.4 to 1.7 were deposited at 120° C. The hydrogen content in the films was in the range of 25-40 atomic %. Generally, the films with higher [N]/[Si] are said to have higher mass density and higher compressive stress. The resistivity of a-SiNx:H films estimated at the field of 1 MV/cm was said to be in the range of 1014-1016 Ohm·cm, and the films with higher [N]/[Si] were said to have a higher breakdown field and dielectric constant than their lower N-content counterparts. A table of data supporting these conclusions is presented.
Compared to higher temperature counterparts, the lower temperature a-SiNx films are characterized by higher hydrogen content. The N-rich films with a hydrogen concentration of about 40% or more exhibit hydrogen bonded predominantly to N atoms, with a high [N]/[Si] ratio achieved solely due to the high concentration of N—H bonds. The TFTs produced on a plastic film substrate at lower temperatures require a higher threshold voltage (4-5 V) than the TFTs produced on glass at the higher temperatures. As a result, the ON current observed for TFTs produced at the lower temperatures is lower. Although the performance properties of these TFTs complies with the requirements for OLED applications, it is apparent that it would be beneficial to lower the threshold voltage of the TFTs produced at the 120° C. temperature.
As indicated above, the performance capabilities of the TFT are a direct result of the structural characteristics of the films formed during fabrication of the TFTs. The structural characteristics of the films depend directly upon the process conditions and relative amounts of precursors which are used during formation of the films which make up the TFTs. As the size of flat panel displays increase, it becomes increasingly difficult to control the uniformity of the individual films produced across the increased surface area. With respect to PECVD deposited silicon-nitride comprising films, which are used either as the gate dielectric layer or as the passivation dielectric layer, control of uniformity of the film across the substrate becomes particularly difficult when the PECVD is carried out in a process chamber having parallel-plate, capacitively coupled electrodes over about 1 m×1 m. At the higher RF power applications, the RF power appears to concentrate at the center of the electrode area, resulting in a dome-shaped thickness profile, and film properties are indicative of the non-uniform power distribution across the electrodes. This kind of phenomena is more pronounced at the higher RF power which is used to obtain film deposition rates (D/R) which are in excess of about 1000 Å/min.
Conventional PECVD processes for producing a-SiNx:H employ a precursor gas mixture which is highly diluted with nitrogen (N2) to obtain desired film properties. Such desired film properties are: a compressive film stress in the range of about 0 to 1×1010 dynes/cm2; low Si—H content of typically less than about 15 atomic %; and a low wet etch rate in HF solution (WER) of less than about 800 Å/min (normalized to thermal oxide at 1000 Å/min). However, a plasma produced at high concentrations of N2 (where N2:SiH4 is greater than 2:1) in the precursor gas produces a particularly non-uniform plasma over a large surface area, for example, a substrate having dimensions larger than about 1000 mm×1000 mm (one square meter). This is believed to be due to the higher energy required to achieve dissociation of N2 molecules. To overcome this problem with respect to the production of flat panel displays having large surface areas, the N2 precursor gas was replaced by NH3 precursor gas, which dissociates more easily.
More recently, there has been increased demand for even larger flat panel displays, for example those with substrates having dimensions larger than about 1500 mm×1800 mm. Initial efforts to produce flat panel displays of this size using a NH3 precursor to supply nitrogen during formation of the a-SiNx:H gate dielectric films resulted in the formation of a-SiNx:H films exhibiting a higher hydrogen content in the film. As discussed above, this higher hydrogen content leads to a higher threshold voltage requirement for the TFT, which is harmful to performance of the TFT. There is presently a need for a process which permits formation of the a-SiNx:H gate dielectric films over large surface area substrates, where the density of the deposited film is consistent across the substrate surface.
Commonly owned, copending U.S. application Ser. No. 10/829,016 (“the '016 application”), filed on Apr. 30, 2004, and entitled “Controlling the Properties and Uniformity of a Silicon Nitride Film by Controlling the Film Forming Precursors”, discloses a method of PECVD depositing an a-SiNx:H dielectric film useful in a TFT device as a gate dielectric, when a series of TFT devices are arrayed over a substrate having a surface area larger than about 1 m2. The method comprises: depositing an a-SiNx:H dielectric film over a substrate which is at a temperature ranging from about 120° C. to about 340° C., at a process chamber pressure which ranges between about 1.0 Torr to about 2.0 Torr, where the a-SiNx:H is deposited from precursors including N2, NH3, and SiH4, and where a component ratio of NH3:SiH4 ranges from about 5.3 to about 10.0, a component ratio of N2:SiH4 ranges from about 5.5 to about 18.7, and a component ratio of N2:NH3 ranges from about 0.6 to about 2.3. A plasma is applied to a mixture of the precursors, so that the plasma density in a process chamber in which the a-SiNx:H dielectric film is deposited ranges between about 0.2 W/cm2 and about 0.6 W/cm2. The film deposition rate is typically more than 1000 Å/min; the Si—H bonded content of the a-SiNx:H film is less than about 15 atomic %; the film stress ranges from about 0 to about −1010 dynes/cm2; the film thickness across the substrate surface area varies by less than about 17%; and, the refractive index (RI) of the film ranges from about 1.85 to about 1.95.